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-- Company: 
-- Engineer:
--
-- Create Date:   09:05:25 11/09/2010
-- Design Name:   
-- Module Name:   E:/Dev/VHDL/state_machine/tb_counter32.vhd
-- Project Name:  state_machine
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: COUNTER32
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tb_counter32 IS
END tb_counter32;
 
ARCHITECTURE behavior OF tb_counter32 IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT COUNTER32
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         load : IN  std_logic;
         seed : IN  std_logic_vector(31 downto 0);
         mod32 : OUT  std_logic;
         end_of_count : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '1';
   signal load : std_logic := '1';
   signal seed : std_logic_vector(31 downto 0) := X"00000031";

 	--Outputs
   signal mod32 : std_logic;
   signal end_of_count : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: COUNTER32 PORT MAP (
          clk => clk,
          reset => reset,
          load => load,
          seed => seed,
          mod32 => mod32,
          end_of_count => end_of_count
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.	
		reset <= '0' after 5ns;
		load <= '0' after 10ns;
      -- insert stimulus here 

      wait;
   end process;

END;
